Integrated circuitry fabrication typically encompasses the patterning of various features relative to substrate material. Examples include trenches, contact openings and subtractive patterning of layers for the formation of circuit devices, such as transistor gates, capacitors, diodes, etc. over underlying material. One common method of patterning features formed by etching includes photolithography. Such typically includes the deposition of a patternable masking layer, commonly known as photoresist. Such materials can be processed to modify their solubility in certain solvents, and thereby are readily usable to form patterns on a substrate. For example, portions of a deposited photoresist layer can be exposed to actinic energy through openings in a mask or reticle to change the solvent solubility of the exposed regions versus the unexposed regions compared to the solubility in the as-deposited state. Thereafter, the exposed or unexposed regions can be removed depending upon the type of photoresist, thereby leaving a masking pattern of the photoresist on the substrate. Adjacent areas of the underlying substrate next to the masked portions can be processed, for example by etching, to form a desired feature in the substrate adjacent the masking material. In certain instances, multiple different layers of photoresists and/or a combination of photoresists with non-radiation sensitivity masking materials are utilized.
Exemplary prior art problems which motivated aspects of the invention are described in connection with FIGS. 1 and 2. Referring initially to FIG. 1, a substrate fragment is indicated generally with reference numeral 10. Such comprises a substrate material 12 to be patterned having a masking layer 14 formed thereover. Substrate 12 typically comprises a semiconductor substrate, and might comprise various insulating, semiconducting and conducting layers formed over a bulk semiconductive material, for example monocrystalline silicon. Alternately by way of example only, substrate 12 might comprise a semiconductor-on-insulator substrate. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
In this particular example, the particular exemplary feature formed within substrate material 12 comprises an opening 16. An opening 18 has been patterned within masking material 14 for the formation of opening 16 in substrate material 12. A desired intent is that the outline of opening 18 formed within masking material 14 be identically duplicated in the etch of material 12 in forming feature 16. However in some instances, opening 18 in material 14 can develop ramped or sloped outer-angling sidewalls 20. High energy etching ions 13 can collide with such surfaces causing displacement of material of masking layer 14 and redeposition on the opposing sidewall, thereby resulting in the exemplary depicted residue 22. Such can result in considerably sloped sidewalls of feature 16 within substrate material 12, and a corresponding decrease in the size of the opening being etched at the bottom of such openings.
FIG. 2 illustrates another typically undesired artifact with respect to a substrate fragment 10a. Like numerals from the FIG. 1 embodiment are utilized where appropriate, with differences being indicated with the suffix “a” or with different numerals. In FIG. 2, high energy ions 13 are depicted as deflecting from sloped surfaces 20 without necessarily displacing the material of masking layer 14, but otherwise hitting opposite sidewalls within material 12. Such can result in the bowed profile regions 24 which also adversely affect the profile of the opening 16a being formed in material 12.
While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.